Integrated circuit (IC) fabrication on a silicon wafer can be thought of as “front end of the line” processing (FEOL) and “back end of the line” processing (BEOL). FEOL processing is frequently the fabrication of various devices on the topside layer of the wafer and BEOL is normally perceived as electrically interconnecting the various devices created in the FEOL processing. Integrated circuits are particularly susceptible to contaminants both during FEOL and BEOL and therefore the wafer goes through numerous cleaning processes during the fabrication process. The contamination can involve large particles that are embedded on the wafer at some level or degree of adhesion. Silicon (Si), silicon dioxide (SiO2) surfaces, and the like are typically cleaned in the FEOL. In contrast, metal layers are present on the wafers during BEOL, and therefore different cleaners of a more limited nature than FEOL cleaners are necessary for BEOL cleaning. The objective of any cleaning process is to remove particles without damaging the wafer.
Lithography is a semiconductor fabrication process that normally involves transferring an electronic pattern to a photoresist on the surface of a semiconductor substrate. Frontside surface contaminants and defects on wafers have been the primary focus of semiconductor manufacturers, whereas little consideration has been focused on backside wafer contaminants. Based on new technology nodes, semiconductor manufacturers have begun centering attention on contaminants located on the backside of the substrate that can have a significant impact on wafer scrap rates, rework, yield, parametric outliers, and the like. Backside cross contamination, for example, can result in zero yield in portions of the wafer due to opens or shorts from pattern defocus, increased rework, decreased throughput, lower wafer yields, and the like.
Potential sources of contamination are poor maintenance of the process line, poor tool design, poor process setup, contamination from incoming wafers, contaminated handling tools, moving wafers from tool to tool, contaminants picked up in a cleaning process, and the like One of the conventional strategies to resolve backside contamination is to perform additional cleaning steps for each wafer patterning loop that are dedicated mainly to cleaning the backside of the wafer. Backside contamination and large particles, in particular, can contribute to lithographic issues to be discussed infra, by causing photolithography “hot spots”, distorting wafer flatness during exposure, and the like. If hot spots are detected during various process steps, for example, wafers have to be reworked at great expense or the wafers can be scrapped which results in a significant reduction in yield.
In conventional memory device fabrication, the wafer backside is often coated with a nitride film. However, nitride is not advantageous with current BEOL cleans that are directed to clean oxide films on the front surface of the wafer. Use of nitride film is not an optimal approach as the majority of industry cleaning processes do not address nitride films. In addition, nitride has a greater affinity for particle adhesion than does oxide.
Therefore in integrated circuit technology and other applications there remains a need to reduce wafer backside contaminants in order to ensure high quality of wafers, high yields of wafers and the like.